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Design Verification Engineer

Location
San Jose, CA, United States

Posted on
Oct 28, 2016

Profile

Design Verification Engineer
Duties:
•
Create high quality test cases and sequences in SystemVerilog/OVM
•
Assist in verification plan development.
•
Utilize advanced verification techniques.
•
Assist with functional coverage development and reporting.
•
Write tools and scripts in Perl and other script languages to enhance the verification process
Qualifications and requirements
•
BS, MS, PhD, in computer science or engineering
•
Experience with an OOP language, SystemVerilog is preferred.
•
PCIE and/or USB experience is highly desired.
•
OVM or related methodology (VMM, eRM, RVM, AVM, etc.) is highly desired.
•
Good software skills in object oriented programming (OOP), C, C , Perl, csh
Location:
San Jose, CA
Duration:
1 year project
Please send your resume to **** for immediate consideration.
Aaron Schneickert
Embedded Resource Group, Inc
3031 Tisch Way
Suite 701
San Jose, CA 95128
****
Web: ****

Company info

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