FPGA Design Engineer

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FPGA Design Engineer
FPGA Design, bring up, debug and verification. Supporting FPGA for testing of an ASIC. Most FPGA RTL code is already developed. Consultant will support and verify RTL code.
Help in lab with debugging of test chip, FPGA and bringup of entire system. Must be comfortable in the lab.
• 10-15 years of experience
• RTL coding in Verilog required, System Verilog is desired.
• Experience with Altera
• Debug experience
• System Design experience
• Board design skills would be highly desired. Experience with Allegro or other similar schematic Capture tools.
Daniel Lewis
Embedded Resource Group, Inc
3031 Tisch Way
Suite 701
San Jose, CA 95128
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Web: ****

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